1. Field of the Invention
This invention relates to a method for improving device design and process flow design in the fabrication of semiconductor devices.
2. Brief Description of the Prior Art
The semiconductor fabrication art is constantly attempting to reduce the cost and cycle time required for semiconductor manufacturing technology development. In this regard, the effect of statistical variations of processing operations during manufacturing on the performance of modern microelectronic devices is becoming an increasingly important issue. Two reasons for the increased significance are, first, that the feature sizes and geometry of deep submicron devices makes device performance very sensitive to small deviations from the desired value and, second, fast time-to-market requires a robust design to minimize parametric yield loss.
The increasing importance of statistical variations makes it necessary to consider manufacturability issues during device and process flow design. The approach taken is modelling and computer analysis to predict the correct or most advantageous process. There are two subapproaches, one being deterministic design, which determines whether the process is feasible at all, and the other being directed toward profitability with improved yield and/or performance being the goal. The present invention is directed to the latter problem, namely profitability.
In the fabrication of semiconductor devices, the fabrication process requires a plurality of processing steps or operations, generally sequential, wherein the result of the same step from device to device will generally vary. To comprehend the impact of these statistical variations during device fabrication on device performance and reliability, a model of the process flow is provided as a sequence of process modules, where each process module is a sequence of contiguous process steps. Each process module transforms the state of the incoming wafer. Mathematically, the state of a wafer can be represented as a vector of all the structure and doping parameters that affect device performance and/or reliability. If W.sub.k is the wafer-state coming into module k, W.sub.k+1 is the wafer-state after completion of the fabrication step performed in module k, F.sub.k is the wafer-state transformation performed by the module and P.sub.k is the vector of process treatments applied at a module, then, ignoring the effect of manufacturing variations, there results the vector equation: W.sub.k+1 =F.sub.k (W.sub.k,P.sub.k). Manufacturing variations make the wafer-state a vector of random variables. The equation for wafer state including wafer state transformations changes to: W.sub.k+1 =F.sub.k (W.sub.k,P.sub.k)+.epsilon. [Equation (1)], where .epsilon. provides the joint distribution of the random variables comprising W.sub.k+1. For example, .epsilon. could be distributed normally with a mean .mu. and covariance matrix .SIGMA..
One prior art method of reducing the impact of process variations is to employ drive to target process control which is unrelated to the invention herein.
Another approach is to design process flows which are robust to manufacturing variations. This approach is known as statistical design. Most prior work on statistical design has focussed on improving circuit design given a certain level of variability in device performance. The work in this area follows two main approaches, these being design centering and sensitivity minimization. Design centering defines an acceptable region of circuit performance and attempts to find a circuit design that minimizes the probability of falling outside the acceptable region for the given variation in device performance. Typical approaches for design centering are based upon the estimation of the acceptability region and Monte Carlo simulation, which are described in "Optimization of parametric yield: A tutorial", by S. W. Director, P. Feldmann and K. Krishna, International Journal of High Speed Electronics, 3(1), pp. 95-136, 1992. A typical approach for sensitivity minimization is to build macromodels like response surfaces of circuit performance in terms of key circuit designables. Sensitivity can then be quickly evaluated and optimized using the macromodels.
Statistical device and flow design has not been as well investigated as statistical circuit design. An approach has been proposed based upon Monte-Carlo process simulation followed by device simulation. This approach makes use of the FABRICS process simulator as discussed in "Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters", by M. A. Styblinski and L. J. Opalski, IEEE Transactions on Computer-Aided Design, CAD-5(1), pp. 79-89 (1986) which allows the typical variation in process inputs to be specified along with the process settings for process simulation. Variability in the device performance induced by the variations in process settings can be estimated by performing a device simulation for each final device structure produced by Monte-Carlo process simulation. Non-linear optimization coupled with device performance variability estimation can be used to find process settings that minimize the sensitivity of device performance to variations in process settings.
The prior art has built response surfaces from process settings to the device performance to estimate the effect of process variation on device performance. These response surfaces could be used with Monte-Carlo simulation and estimates of variability in process settings to estimate the variability in device performance.
The difficulty with the above approaches is that variability estimates are required in terms of the process inputs and this estimate is difficult to achieve. It is much easier to estimate the variability in process outputs because they can be measured directly. For example, it is much easier to estimate variability in gate-length, either optically or electrically, than to measure variability in lithography process settings such as exposure dose, mask misalignment, etc. Another disadvantage of modeling device performance in terms of process settings is that coverage of a large number of process inputs requires extremely large numbers of simulations. It is therefore apparent that improved techniques are required.